Title :
Fringing Field Effects in Thin-Film Silicon Transistors on Glass
Author :
Nassar, Christopher James ; Revelli, Joseph F., Jr. ; Williams, Carlo A Kosik ; Bowman, Robert John
Author_Institution :
Dept. of Electr. Eng., Rochester Inst. of Technol., Rochester, NY, USA
Abstract :
A new process enabling the transfer of a single-crystal silicon film to a glass substrate has been developed allowing for the creation of fully crystalline thin-film silicon-on-glass (SiOG) transistors. The dominant 2-D effect in SiOG transistors results from fringing electric field lines emanating through the glass substrate between the source, drain, and thin-film channel regions. The fringing field leads to a shift in the flatband or threshold voltage in a similar manner to drain-induced barrier lowering. The fringing field effect can lead to an 11% shift in flatband for devices with channel length of 4 μm and a nominal flatband of -1 V. A compact model for the fringing field in these devices has been developed using conformal mapping techniques that capture the dependence on both channel length and the relative size of the source and drain electrodes. The model accurately predicts the influence of the fringing field on subthreshold drain current for SiOG PFETs operating in accumulation. The model is validated against the 2-D device simulator Silvaco Atlas.
Keywords :
glass; silicon-on-insulator; thin film transistors; 2D device simulator; Si-SiO2; SiOG transistors; Silvaco Atlas; channel length; conformal mapping techniques; dominant 2D effect; drain electrodes; drain-induced barrier lowering; flatband voltage; fringing electric field lines; fringing field effects; fully crystalline thin-film silicon-on-glass transistors; glass substrate; single-crystal silicon film; source electrodes; subthreshold drain current; thin-film channel regions; thin-film silicon transistors; threshold voltage; voltage -1 V; Conformal mapping; Crystallization; FETs; Glass; Semiconductor films; Semiconductor thin films; Silicon; Substrates; Thin film transistors; Threshold voltage; CMOS; drain-induced barrier lowering (DIBL); fringing field; modeling; semiconductor modeling; silicon-on-insulator (SOI); thin-film transistors (TFTs);
Journal_Title :
Display Technology, Journal of
DOI :
10.1109/JDT.2010.2052348