Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor

In this study, the authors present a floating-point synthetic aperture radar processor that achieves a power efficiency of 18.0 mW/GFlop in simulation through the use of three-dimensional (3D) integration and reconfiguration of the data path. The reconfiguration reduces the number of arithmetic units required in every processing element (PE) from 24 down to 10. The processor uses a 3D integrated memory that reduces the memory power consumption by 70 when compared to a 2D memory. The system processes a SAR image using a two-tier 3D integrated PE, which when compared to an equivalent 2D PE decreases the power consumed in the interconnect of each PE by 15.5 and the footprint by 49.2 , and allows the PE to operate 7.1 faster in simulation. Additionally, by using 3D integration in the memory one can reduce the power consumption of the memory by 70 . Furthermore, the authors show how the 3D aspects of the processor can be realised by using 2D tools, when used in conjunction with the proposed through-silicon via assignment algorithm.