Title :
Low delta-I noise CMOS circuits based on differential logic and current limiters
Author :
González, Jose Luis ; Rubio, Antonio
Author_Institution :
Dept. d´´Eng. Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
fDate :
7/1/1999 12:00:00 AM
Abstract :
Switching noise is becoming an important constraint in mixed signal design. In this paper we present an approach to implement combinational circuits that generate low levels of delta-I noise by obtaining a trapezoidal current waveform shape. We use a differential logic (ECDL) together with current limiters to implement a 4×4 multiplier. We present the results of the simulation of this multiplier and the comparison with the static complementary-metal-oxide semiconductor (CMOS) implementation
Keywords :
CMOS logic circuits; combinational circuits; current limiters; digital arithmetic; integrated circuit design; integrated circuit noise; logic design; multiplying circuits; ECDL; combinational circuits; current limiters; design method; differential logic; low delta-I noise CMOS circuits; multiplier implementation; switching noise; trapezoidal current waveform shape; CMOS logic circuits; Circuit noise; Combinational circuits; Multi-stage noise shaping; Noise generators; Noise level; Noise shaping; Semiconductor device noise; Shape; Signal design;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
