Hardware design for modern radar processing

Author

Bierens, L.H.J.

Author_Institution

TNO Phys. & Electron. Lab., The Hague, Netherlands

Volume

9

Issue

6

fYear

1997

fDate

12/1/1997 12:00:00 AM

Firstpage

257

Lastpage

270

Abstract

Programmability and flexibility are often emphasised in today´s hardware design for modern radar processing, but in many radar applications this does not lead to the desired optimum hardware solution, especially if application-specific requirements, such as limited processor size and power consumption combined with extremely high throughputs, play a key role. Many parts of a radar processing system can be optimised if dedicated hardware solutions are permitted for the so-called `bulk-processing´, which requires a low degree of flexibility and has a high algorithmic regularity. In this paper some arguments are given in favour of combined programmable/dedicated-hardware solutions for radar processing applications, supported by illustrative application and design examples

Keywords

digital signal processing chips; programmable logic devices; radar applications; radar computing; radar signal processing; DSP chip; algorithmic regularity; bulk-processing; hardware design; high throughputs; power consumption; processor size; programmable/dedicated hardware solutions; radar processing applications; radar processing system;

fLanguage

English

Journal_Title

Electronics & Communication Engineering Journal

Publisher

iet

ISSN

0954-0695

Type

jour

DOI

10.1049/ecej:19970604

Filename

649123