DocumentCode :
1527972
Title :
Effect of cleaning and non-cleaning situations on the reliability of flip-chip packages
Author :
Wang, Jianjun ; Ren, Wei ; Zou, Daqing ; Liu, Sheng
Author_Institution :
Dept. of Mech. Eng., Wayne State Univ., Detroit, MI, USA
Volume :
22
Issue :
2
fYear :
1999
fDate :
6/1/1999 12:00:00 AM
Firstpage :
221
Lastpage :
228
Abstract :
A combined experimental and numerical study is conducted to investigate whether the reliability of flip-chip solder interconnects is affected by noncleaning situations, in which underfill cannot be completely filled in the corners of the solder balls because of contamination like flux residues subsisting on those parts after solder reflow. The real-time moire interferometry technique is used to measure the warpage (deformation) for the selected “cleaning” and “noncleaning” flip-chip package specimens during the test, while a nonlinear finite element technique, in which the viscoplastic material properties of solder balls and underfill are considered, is adapted to simulate the corresponding “cleaning” and “noncleaning” situations to assess the impact on solder interconnect reliability. The noncleaning situation is in contrast to the cleaning situation considered by many researchers. The results indicate that there is no obvious difference for the warpage obtained by either the test data or the numerical work between the cleaning samples and the noncleaning samples. However, the simulation results of the stresses (strains) reveal that the noncleaning situation decreases the mechanical stability and shortens the life time of those flip-chip packages to a level well below the predictions of the cleaning simulations. The fatigue life in some points of the outmost solder joint predicted by using the cleaning FE models is much higher than that predicted by using the noncleaning PE models. Since it is hard to find perfect filled layers for any real world samples, the cleaning model yields overly conservative results. In addition, the predicted deformation values of the flip-chip package obtained from the finite element analysis are also compared with the test data obtained from the laser moire interferometry technique. Good agreement is obtained. In particular, the displacement contours of the flip-chip package samples both in the s and y directions obtained from the test show similar distribution patterns compared with those modeled by the finite element method
Keywords :
fatigue; finite element analysis; flip-chip devices; integrated circuit packaging; integrated circuit reliability; light interferometry; moire fringes; reflow soldering; surface cleaning; viscoplasticity; cleaning; deformation values; displacement contours; fatigue life; flip-chip packages; flux residues; interconnect reliability; mechanical stability; noncleaning situations; nonlinear finite element technique; real-time moire interferometry technique; reliability; solder reflow; viscoplastic material properties; warpage; Cleaning; Contamination; Deformable models; Finite element methods; Interferometry; Material properties; Materials testing; Packaging; Pollution measurement; Predictive models;
fLanguage :
English
Journal_Title :
Components and Packaging Technologies, IEEE Transactions on
Publisher :
ieee
ISSN :
1521-3331
Type :
jour
DOI :
10.1109/6144.774735
Filename :
774735
Link To Document :
بازگشت