Title :
Corrections to “Unified Logical Effort—A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect” [May 10 689-696]
Author :
Morgenshtein, Arkadiy ; Friedman, Eby G. ; Ginosar, Ran ; Kolodny, Avinoam
Abstract :
In the above titled paper (ibid., vol. 18, no. 5, pp. 689-696, May 10), the formula and the caption in Fig. 3 appeared incorrectly. The correct figure is presented here along with an explanation.
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2010.2052421
