Author_Institution :
Dept. of Comput. Software, Aizu Univ., Wakamatsu, Japan
Abstract :
This paper makes two contributions toward computing unique input/output (UIO) sequences in finite-state machines. Our first contribution is to compute all UIO sequences of minimal lengths in a finite-state machine. Our second contribution is to present a generally efficient algorithm to compute a UIO sequence for each state, if it exists. We begin by defining a path vector, vector perturbation, and UIO tree. The perturbation process allows us to construct the complete UIO tree for a machine. Each sequence of input/output from the initial vector of a UIO tree to a singleton vector represents a UIO sequence. Next, we define the idea of an inference rule that allows us to infer UIO sequences of a number of states from the UIO sequence of some state. That is, for a large class of machines, it is possible to compute UIO sequences for all possible states from a small set of initial UIOs. We give a modified depth-first algorithm, called the hybrid approach, that computes a partial UIO tree, called an essential subtree, from which UIO sequences of all possible states can be inferred. Using the concept of projection machines, we show that sometimes it is unnecessary to construct even a partial subtree. We prove that if a machine remains strongly connected after deleting all the converging transitions, then all of the states have UIO sequences. To demonstrate the effectiveness of our approach, we develop a tool to perform experiments using both small and large machines
Keywords :
finite state machines; formal specification; inference mechanisms; protocols; sequences; trees (mathematics); UIO sequences; UIO tree; converging transitions; essential subtree; finite state machines; hybrid approach; inference rule; modified depth-first algorithm; partial UIO tree; path vector; perturbation process; projection machines; singleton vector; unique input/output sequences; vector perturbation; Circuit testing; Communication system control; Costs; Data communication; Hardware; Inference mechanisms; Interference; Program processors; Protocols; Sequential circuits;