DocumentCode :
1528147
Title :
Speeding Up Physical Synthesis with Transactional Timing Analysis
Author :
Papa, David ; Moffitt, Michael D. ; Alpert, Charles J. ; Markov, Igor L.
Volume :
27
Issue :
5
fYear :
2010
Firstpage :
14
Lastpage :
25
Abstract :
Modern physical-synthesis flows operate on very large designs and perform increasingly aggressive timing optimizations. Traditional incremental timing analysis now represents the single greatest bottleneck in such optimizations and lacks the features necessary to support them efficiently. This article describes a paradigm of transactional timing analysis, which, together with incremental updates, offers an efficient, nested undo functionality that avoids significant timing calculations.
Keywords :
application specific integrated circuits; integrated circuit design; timing; application specific integrated circuits; incremental timing analysis; physical synthesis; transactional timing analysis; Algorithm design and analysis; Circuit optimization; Design engineering; Design optimization; Engines; Performance analysis; Runtime; Software algorithms; Software design; Timing; algorithms; design and test; physical synthesis; static timing analysis; timing-driven placement; transactional timing analysis;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2010.76
Filename :
5499453
Link To Document :
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