Title :
A &thetas;(1) algorithm for modulo addition
Author :
Elleithy, Khaled M. ; Bayoumi, Magdy A.
Author_Institution :
Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
fDate :
5/1/1990 12:00:00 AM
Abstract :
A θ(1) algorithm for large modulo addition for architectures based on the residue number (RNS) is proposed. The addition is done in a fixed number of stages which does not depend on the size of the modulus. The proposed modulo adder is much faster than previous adders and more area efficient. The implementation of the adder is modular and is based on simple cells, which leads to efficient VLSI realization
Keywords :
VLSI; adders; digital arithmetic; &thetas;(1) algorithm; area efficient; efficient VLSI realization; modulo adder; modulo addition; residue number; Adders; Arithmetic; Circuits and systems; Computer architecture; Digital filters; Fast Fourier transforms; Filtering; Signal processing algorithms; Table lookup; Very large scale integration;
Journal_Title :
Circuits and Systems, IEEE Transactions on
