Digit-serial processing techniques

Author

Hartley, Richard ; Corbett, Peter

Author_Institution

General Electric Res. & Dev. Center, Schenectady, NY, USA

Volume

37

Issue

6

fYear

1990

fDate

6/1/1990 12:00:00 AM

Firstpage

707

Lastpage

719

Abstract

An architecture is presented for hard-wired data-flow algorithms which is based on the transmission of arithmetic data one digit at a time serially, and performance of operations digit-serially on that data. It is shown that digit-serial computation gives rise to particularly efficient chip designs, and that choice of digit-size allows the user to match throughput requirements to specifications. Details of the implementation of the individual operators as a cell-library of silicon CMOS circuits are given and mention is made of the software environment (silicon compiler) which allows the rapid translation of algorithms to integrated circuits

Keywords

CMOS integrated circuits; circuit layout CAD; digital arithmetic; digital filters; digital signal processing chips; pipeline processing; CMOS circuits; FIR filter; Si; VLSI; cell-library; digit-serial computation; hard-wired data-flow algorithms; integrated circuits; pipeline processing; software environment; Adders; Arithmetic; Chip scale packaging; Circuits; Computer architecture; Latches; Silicon compiler; Software algorithms; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.55029

Filename

55029