DocumentCode :
1528595
Title :
A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video
Author :
Yuan-Hsin Liao ; Gwo-Long Li ; Tian-Sheuan Chang
Author_Institution :
PixArt Imaging, Inc., Hsinchu, Taiwan
Volume :
22
Issue :
11
fYear :
2012
Firstpage :
1604
Lastpage :
1610
Abstract :
To satisfy the heavy performance requirement in real-time high-resolution H.264/AVC, very large-scale integrated implementation of the entropy decoder is necessary since it dominates the overall decoder throughput. In this paper, we propose a high-throughput delay balanced two-level context-based adaptive variable length coding (CAVLC) decoder with 21% shorter critical path delay in comparison to the traditional two-level decoder design. Furthermore, redundant decoding processes are removed by a skipping mechanism. The proposed CAVLC decoder only needs 127.13 cycles per macroblock on average to support level 5.1 decoding with 13.54k gate counts under 90-nm CMOS technology.
Keywords :
CMOS integrated circuits; data compression; decoding; video coding; CMOS technology; critical path delay; entropy decoder; frequency 385 MHz; gate delay balanced two-level CAVLC decoder; high-throughput delay balanced two-level CAVLC decoder; high-throughput delay balanced two-level context-based adaptive variable length coding decoder; real-time high-resolution H.264-AVC; redundant decoding processes; size 90 nm; skipping mechanism; two-level decoder design; ultraHD H.264-AVC video; Decoding; Delay; Encoding; Throughput; Video coding; Context-adaptive variable length decoder (CAVLD); H.264;
fLanguage :
English
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8215
Type :
jour
DOI :
10.1109/TCSVT.2012.2202081
Filename :
6209405
Link To Document :
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