• DocumentCode
    1528790
  • Title

    Computing signal delay in general RC networks by tree/link partitioning

  • Author

    Chan, Pak K. ; Karplus, Kevin

  • Author_Institution
    Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
  • Volume
    9
  • Issue
    8
  • fYear
    1990
  • fDate
    8/1/1990 12:00:00 AM
  • Firstpage
    898
  • Lastpage
    902
  • Abstract
    Most RC simulators handle only tree networks, not arbitrary networks. An algorithm is presented for computing signal delays in general RC networks using the RC-tree computation as the primary operation. The algorithm partitions a given network into a spanning tree and links. It computes the signal delay of the spanning tree, and updates the signal delay as it incrementally adds the links back to reconstruct the original network. If m is the number of links, this algorithm requires m(m+1)/2 updates and m+1 tree delay evaluations. All the tree delay evaluations involve computing signal delays with the same resistive spanning tree, but with different values for the capacitors
  • Keywords
    MOS integrated circuits; circuit CAD; digital integrated circuits; logic CAD; MOS circuits modelling; RC networks; RC simulators; RC-tree computation; arbitrary networks; computing signal delays; links; spanning tree; tree delay evaluations; tree/link partitioning; Adders; Circuits; Computational modeling; Computer networks; Delay effects; Delay estimation; Intelligent networks; MOS capacitors; Partitioning algorithms; Propagation delay;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.57781
  • Filename
    57781