Effects of Dielectric Constant on the Performance of a Gate All Around InAs Nanowire Transistor

The effects of gate dielectric constant on the performance of a gate all around indium arsenide (InAs) nanowire transistor are studied using a 3-D quantum simulation. The replacement of SiO by a high- dielectric improves the OFF-state current, the ON-state current, the ON/OFF current ratio, the inverse subthreshold slope, the channel transconductance, and the switching delay and degrades the power-delay product. The OFF-state current is mainly tunneling current and the high- gate dielectrics improve the device OFF-state performance by increasing the tunnel barrier length. On the other hand, the ON-state current is mainly thermal current and the high- dielectrics improve the device ON-state performance by reducing the barrier height. The gate capacitance is increased with high- dielectrics. However, the improved ON-state current with high- dielectrics makes the switching delay shorter and increases the power (V I) dissipation and power-delay product. Due to very small effective mass of electron in InAs, the quantum effect on threshold voltage is strong and the device with smaller cross section shows better ON-OFF and switching performance at the same gate overdrive voltage.