A novel partially parallel architecture for high-throughput LDPC Decoder for DVB-S2

This paper proposes a high-throughput LDPC (Low-Density Parity-Check) decoder architecture for DVB-S2, the second generation standard for European satellite digital video broadcasting system adopted for HDTV services. In the proposed decoder architecture, a unified processing module, B/CFM (Bitnode/Checknode Functional Module), is designed, which performs the computations both at bitnodes and at checknodes for maximal sharing of hardware resource. It performs the computations at bitnodes clustered into a group and at checknodes clustered also into a group sequentially. The B/CFMs replace the BFMs (Bitnode Functional Module) and CFMs (Checknode Functional Module) used in previous architecture, thus resulting to an increase in throughput. To support parallel data accesses by these B/CFMs, data aligner is designed and placed in front of input port of each memory bank. Experimental results of the proposed architecture exhibit the throughput of 1,020 Mbps, 95.8% improvements over previous architecture, with 25.2% increase in area.