Low-cost testing of high-density logic components

Author

Bassett, Robert W. ; Butkus, Barry J. ; Dingle, Stephen L. ; Faucher, Marc R. ; Gillis, Pamela S. ; Panner, Jeannie H. ; Petrovick, John G., Jr. ; Wheater, Donald L.

Author_Institution

IBM Corp., Essex Junction, VT, USA

Volume

7

Issue

2

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

15

Lastpage

28

Abstract

The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM´s high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The tester´s design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches.<>

Keywords

CMOS integrated circuits; logic testing; CMOS ASIC; boundary-scan; built-in self-test logic; embedded memory arrays; high-density logic components; logic-device tester; low cost testing; testing strategy; weighted random-pattern logic testing; Application specific integrated circuits; Automatic testing; Built-in self-test; CMOS logic circuits; CMOS memory circuits; Circuit testing; Integrated circuit testing; Logic arrays; Logic design; Logic testing;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/54.53042

Filename

53042