Title :
Implementing macro test in silicon compiler design
Author :
Beenker, Frans ; Dekker, Rob ; Stans, Rudi ; Van Der Star, Max
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fDate :
4/1/1990 12:00:00 AM
Abstract :
A testability strategy for a complex VLSI device that is implemented in the Piramid digital-signal-processor silicon compiler is presented. The macro test method proposed supports built-in self-test, scan test, restricted partial scan, and test-control logic at various levels in the design hierarchy. The strategy uses techniques such as a macro test plan, transfer information, and intermediate vector storage. The overhead from adding testability is only 10% of the total area and test-program generation is done with 100% fault coverage in a very short time, since there is no need for global test-pattern generation. A set of tools that guide the testability implementation from design to the final test program is described.<>
Keywords :
VLSI; automatic testing; circuit layout CAD; integrated circuit testing; Piramid digital-signal-processor; built-in self-test; complex VLSI device; design hierarchy; global test-pattern generation; intermediate vector storage; macro test; restricted partial scan; scan test; silicon compiler design; test-control logic; testability strategy; transfer information; Automatic testing; Circuit faults; Circuit testing; Integrated circuit testing; Logic testing; Process design; Signal processing algorithms; Silicon compiler; System testing; Very large scale integration;
Journal_Title :
Design & Test of Computers, IEEE
