Title :
Exploiting instruction- and data-level parallelism
Author :
Espasa, Roger ; Valero, Mateo
Author_Institution :
Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
Simultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to executing 15 to 26 scalar instructions/cycle for numerical applications
Keywords :
parallel architectures; performance evaluation; vector processor systems; data-level parallelism; instruction-level parallelism; performance; simultaneous multithreaded; vector architectures; Clocks; Computer aided instruction; Delay; Multithreading; Out of order; Parallel processing; Random access memory; Registers; Wire; Yarn;
Journal_Title :
Micro, IEEE
