Abstract :
Clearly, instruction issue and execution are closely related: The more parallel the instruction execution, the higher the requirements for the parallelism of instruction issue. Thus, we see the continuous and harmonized increase of parallelism in instruction issue and execution. This article focuses on superscalar instruction issue, tracing the way parallel instruction execution and issue have increased performance. It also spans the design space of instruction issue, identifying important design aspects and available design choices. The article also demonstrates a concise way to represent the design space using DS trees, reviews the most frequently used issue schemes, and highlights trends for each design aspect of instruction issue
Keywords :
instruction sets; parallel architectures; performance evaluation; DS trees; instruction issue; parallel instruction execution; parallelism; performance; superscalar; Computational modeling; Concatenated codes; Concurrent computing; Dynamic scheduling; Feeds; Processor scheduling; Reduced instruction set computing; Tree graphs; VLIW; Workstations;
