Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS

Author

Djahanshahi, Hormoz ; Hansen, Flemming ; Salama, C. André T

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

34

Issue

8

fYear

1999

fDate

8/1/1999 12:00:00 AM

Firstpage

1074

Lastpage

1083

Abstract

This paper presents high-speed differential input and output (I/O) interface circuits for gigabit-per-second serial data communication. The circuits are implemented in a 3.3-V/0.35-μm CMOS process. Signal levels are compatible with industry standards for low-voltage positive emitter-coupled logic (ECL), with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pullups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. Combining circuit techniques with the features of a submicrometer technology, the presented I/O blocks enable a full-CMOS chip to communicate with high-speed ECL-compatible systems and ease up a common I/O-related speed bottleneck. The circuits operate at 622 Mb/s (OC-12) and 1.24 Gb/s (OC-24) in a repeater and a retimer configuration. The asynchronous performance of the receiver and the transmitter was tested at rates up to 2.5 Gb/s

Keywords

CMOS digital integrated circuits; data communication equipment; emitter-coupled logic; high-speed integrated circuits; low-power electronics; 0.35 micron; 1.24 Gbit/s; 2.5 Gbit/s; 3.3 V; 622 Mbit/s; CMOS input-output interface; asynchronous circuit; data communication; emitter coupled logic; high-speed differential circuit; low-voltage circuit; repeater; retimer; CMOS logic circuits; CMOS process; CMOS technology; Circuit testing; Data communication; Integrated circuit interconnections; Pulse circuits; Repeaters; Transmitters; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.777105

Filename

777105