A 5-ns 1-Mb ECL BiCMOS SRAM

Author

Takada, Masahide ; Nakamura, Kazuyuki ; Takeshima, Toshio ; FURUTA, Kouichirou ; Yamazaki, Tohru ; Imai, Kiyotaka ; OHI, Susumu ; Sekine, Yumi ; Minato, Yukio ; Kimuto, H.

Author_Institution

NEC Corp., Kanagawa, Japan

Volume

25

Issue

5

fYear

1990

fDate

10/1/1990 12:00:00 AM

Firstpage

1057

Lastpage

1062

Abstract

A 1-Mword×1-b ECL (emitter coupled logic) 10 K I/O (input/output) compatible SRAM (static random-access memory) with 5-ns typical address access time has been developed using double-level poly-Si, double-level metal, 0.8-μm BiCMOS technology. To achieve 5-ns address access time, high-speed X-address decoding circuits with wired-OR predecoders and ECL-to-CMOS voltage-level converters with partial address decoding function and sensing circuits with small differential signal voltage swing were developed. The die and memory cell sizes are 16.8 mm×6.7 mm and 8.5 μm×5.3 μm, respectively. The active power is 1 W at 100-MHz operation

Keywords

BIMOS integrated circuits; SRAM chips; emitter-coupled logic; 0.8 micron; 1 Mbit; 100 MHz; 5 ns; BiCMOS technology; ECL; ECL-to-CMOS voltage-level converters; SRAM; address access time; double-level metal; double-level poly-Si; emitter coupled logic; high-speed X-address decoding circuits; partial address decoding function; polycrystalline Si; polysilicon; static random-access memory; wired-OR predecoders; BiCMOS integrated circuits; Decoding; Delay effects; Driver circuits; MOSFET circuits; Random access memory; SRAM chips; Signal processing; Voltage; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62124

Filename

62124