DocumentCode
1532846
Title
nand Gate Design for Ballistic Deflection Transistors
Author
Wolpert, David ; Diduck, Quentin ; Ampadu, Paul
Author_Institution
Univ. of Rochester, Rochester, NY, USA
Volume
10
Issue
1
fYear
2011
Firstpage
150
Lastpage
154
Abstract
This paper presents a nand gate designed using ballistic deflection transistors (BDTs). Room temperature BDT measurements are captured in an empirical device model to simulate multi-BDT logic design. Measurements from a fabricated BDT nand gate validate the multidevice model and demonstrate the promise of BDTs for nanoscale circuit design.
Keywords
ballistic transport; logic design; logic gates; nanoelectronics; semiconductor device measurement; semiconductor device models; BDT NAND gate; NAND gate design; multiBDT logic design; multidevice model; nanoscale circuit design; room temperature ballistic deflection transistor measurement; temperature 293 K to 298 K; 2-D electron gas (2-DEG); Ballistic transport; device model; logic design; quasi-ballistic transport;
fLanguage
English
Journal_Title
Nanotechnology, IEEE Transactions on
Publisher
ieee
ISSN
1536-125X
Type
jour
DOI
10.1109/TNANO.2009.2034962
Filename
5306176
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