Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-Å gate oxide MOSFETs

Author

Ahmed, Khaled ; Ibok, Effiong ; Yeap, Geoffrey C F ; Xiang, Qi ; Ogle, Bob ; Wortman, Jimmie J. ; Hauser, John R.

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

Volume

46

Issue

8

fYear

1999

fDate

8/1/1999 12:00:00 AM

Firstpage

1650

Lastpage

1655

Abstract

This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-Å oxide MOS devices, transistors with channel lengths less than about 10 μm will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance

Keywords

MOSFET; capacitance; elemental semiconductors; inversion layers; semiconductor device testing; silicon; tunnelling; 10 micron; MOSFETs; Si; capacitance-voltage analysis; channel inversion layer charge; channel lengths; channel resistance; extrinsic capacitance roll-off; finite channel resistance; gate oxide; nonnegligible gate tunneling current; polysilicon-gate depletion; strong inversion; terminal capacitance; test structures; transmission-line-model; tunnel currents; ultrathin gate oxides; Attenuation; Capacitance measurement; Conductivity measurement; Doping; Frequency measurement; Impedance measurement; MOSFET circuits; Parasitic capacitance; Testing; Tunneling;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.777153

Filename

777153