Selection of a resolver-to-angle conversion algorithm

A paradigm is presented for the selection of an algorithm for implementation in dedicated hardware. The particular application considered is a gate-array implementation of a resolver-to-angle converter. Desirable attributes included accuracy, power consumption, and speed. The algorithm selection proceeds in two phases. Six candidate algorithms are qualitatively evaluated. Three are rejected and the remaining algorithms are subjected to detailed computer simulations in order to arrive at the optimal choice for this application. This final selection, interestingly enough, is not the one initially thought to be optimal.