DocumentCode
1533136
Title
A 15-ns 4-Mb CMOS SRAM
Author
Aizaki, Shingo ; Shimizu, Toshiyuki ; Ohkawa, Masay Oshi ; Abe, Kazuhiko ; Aizaki, Akane ; Ando, Manabu ; Kudoh, Osamu ; Sasaki, Isao
Author_Institution
NEC Corp., Kanagawa, Japan
Volume
25
Issue
5
fYear
1990
fDate
10/1/1990 12:00:00 AM
Firstpage
1063
Lastpage
1067
Abstract
A 4-Mb SRAM with a 15-ns access time and a uniquely selectable (×4 or ×1) bit organization has been developed based on a 0.55-μm triple-polysilicon double-metal CMOS technology. An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (TDW) are three key circuits which have been utilized in addition to the 0.55-μm CMOS technology to achieve the remarkable access time of 15 ns. Bit organization of either ×4 or ×1 can be selected purely electrically, and does not require any pin connection procedure
Keywords
CMOS integrated circuits; SRAM chips; 0.55 micron; 15 ns; 4 Mbit; CMOS SRAM; Si; Y-controlled bit-line loads; electrically selectable bit organisation; input-controlled PMOS-load; sense amplifier; static RAM; transfer word driver; triple-polysilicon double-metal; Application software; CMOS memory circuits; CMOS technology; Circuit testing; Decoding; Driver circuits; Helium; Large-scale systems; Mirrors; Random access memory;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.62125
Filename
62125
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