Title :
Modeling and Design of Ferroelectric MOSFETs
Author :
Chen, Han-Ping ; Lee, Vincent C. ; Ohoka, Atsushi ; Xiang, Jie ; Taur, Yuan
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, CA, USA
Abstract :
A drain-current model has been developed for ferroelectric metal-oxide-semiconductor field-effect transistors by coupling Pao-Sah double integral with the nonlinear Landau description of the field and polarization of ferroelectric insulators. The resultant solution for surface potential ψs versus gate voltage Vg consists of double hysteresis loops sensitive to the ferroelectric-insulator thickness. With a proper choice of the ferroelectric-film thickness, the hysteresis shape can be tailored for operating voltages below 0.5 V, e.g., at VDD = 0.25 V, with a drain-current slope steeper than the reciprocal of 60 mV/dec beyond the threshold voltage.
Keywords :
MOSFET; dielectric hysteresis; dielectric polarisation; ferroelectric devices; insulators; semiconductor device models; Pao-Sah double integral; double hysteresis loops; drain-current model; drain-current slope steeper; ferroelectric MOSFET; ferroelectric insulators; ferroelectric metal-oxide-semiconductor field-effect transistors; ferroelectric-film thickness; ferroelectric-insulator thickness; gate voltage; hysteresis shape; nonlinear Landau description; polarization; resultant solution; surface potential; threshold voltage; Capacitance; Electric potential; Hysteresis; Logic gates; MOSFETs; Tin; Ferroelectric devices; low-power electronics; metal–oxide–semiconductor field-effect transistor)s (MOSFETs); negative capacitance devices;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2011.2155067
