A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture

Author

Hirose, Toshihiko ; Kuriyama, Hirotada ; Murakami, Shuji ; Yuzuriha, Kojiro ; Mukai, Takao ; Tsutsumi, Kazuhito ; Nishimura, Yasumasa ; Kohno, Yoshio ; Anami, Kenji

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

25

Issue

5

fYear

1990

fDate

10/1/1990 12:00:00 AM

Firstpage

1068

Lastpage

1074

Abstract

A 20 ns 4-Mb CMOS SRAM operating at a single supply voltage of 3.3 V is described. The fast access time has been achieved by a newly proposed word-decoding architecture and a high-speed sense amplifier combined with the address transition detection (ATD) technique. The RAM has the fast address mode, which achieves quicker than 10-ns access, and the 16-b parallel test mode for the reduction of test time. A 0.6-μm process technology featuring quadruple-polysilicon and double-metal wiring is adopted to integrate more than 16 million transistors in a 8.35-mm×18.0-mm die

Keywords

CMOS integrated circuits; SRAM chips; decoding; 0.6 micron; 10 ns; 20 ns; 3.3 V; 4 Mbit; CMOS SRAM; address transition detection; double-metal wiring; fast address mode; hierarchical word decoding architecture; high-speed sense amplifier; parallel test mode; polycrystalline Si; quadruple-polysilicon; single supply voltage; static RAM; Circuit testing; Decoding; Helium; Pulse amplifiers; Pulse generation; Random access memory; Read-write memory; Transistors; Voltage; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62126

Filename

62126