A 4-ns BiCMOS translation-lookaside buffer

Author

Tamura, Leilani R. ; Yang, Tsen-Shau ; Wingard, Drew E. ; Horowitz, Mark A. ; Wolley, B.A.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

Volume

25

Issue

5

fYear

1990

fDate

10/1/1990 12:00:00 AM

Firstpage

1093

Lastpage

1101

Abstract

A 64-entry fully associative TLB (translation-lookaside buffer) with a pin-to-pin translation delay of 3.6 ns is described. This translation speed is achieved by using BiCMOS content-addressable memory (CAM) and SRAM arrays wherein small signal swings are maintained throughout the critical translation path. A BiCMOS CAM cell that uses a single bipolar translator to drive the match line is introduced. The TLB has been integrated as a stand-alone chip in an 0.8-μm BiCMOS technology. The circuit operates from a 5.2-V supply with ECL-compatible input and output levels. The power dissipation (excluding the power dissipated in the physical address output buffers) is less than 600 mW

Keywords

BIMOS integrated circuits; SRAM chips; buffer storage; content-addressable storage; integrated memory circuits; 0.8 micron; 4 ns; 5.2 V; 600 mW; BiCMOS; CAM cell; ECL-compatible input; content-addressable memory; fully associative TLB; power dissipation; single bipolar translator; stand-alone chip; translation-lookaside buffer; BiCMOS integrated circuits; Bipolar transistors; CADCAM; Computer aided manufacturing; Coupling circuits; Delay; Latches; Memory management; Random access memory; Signal design;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62129

Filename

62129