Author :
Kitsukawa, Goro ; Yanagisawa, Kazumasa ; Kobayashi, Yutaka ; Kinoshita, Yoshitaka ; Ohta, Tatsuyuki ; Udagawa, Tetsu ; Miwa, Hitoshi ; Miyazawa, Hiroyuki ; Kawajiri, Yoshiki ; Ouchi, Yoshiaki ; Tsukada, Hiromi ; Matsumoto, Tetsuro ; Itoh, Kiyoo
Abstract :
A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm2, in spite of a 1.3-μm lithography level
Keywords :
BIMOS integrated circuits; DRAM chips; 1 Mbit; 1.3 micron; 23 ns; BiCMOS DRAM; NMOS differential circuit; direct sensing technique; dynamic RAM; high-speed characteristics; memory IC; nonaddress-multiplexing configuration; Application software; BiCMOS integrated circuits; Driver circuits; Helium; Laboratories; Lithography; MOS devices; Microprocessors; Random access memory; Timing;
