Functional Yield Estimation of Carbon Nanotube-Based Logic Gates in the Presence of Defects

Carbon nanotube field-effect transistor (CNFET) is one of the most promising candidates for a building block of post silicon era integrated circuits. One of the major challenges faced by the CNFET is the presence of unwanted metallic tubes that adversely impacts the delay, power, and functional yield of carbon nanotube (CNT) based circuits. In this paper, we present tradeoff between these parameters with the help of Monte Carlo simulations for basic logic gates designed using four different configurations of CNFET including two stacking configurations that we originally proposed in 2008. We present newly developed analytical models to estimate the functional yield of logic gates designed using four different configurations of CNFET. The absolute difference in functional yield magnitudes between the Monte Carlo simulations and analytical models for different percentage of metallic tubes and different drive strength of logic gates is 0% to 0.9% for inverter and 0% to 2.5% for NAND/NOR gates. Results indicate that the proposed stacking configurations have the potential to increase the functional yield by as much as 2X for inverter and 10X for NAND gate. This increase in functional yield was observed for 10X lower static power and for 4.1X-4AX delay penalty under iso-input capacitance.