Title :
Spurious source/drain underlap of large junction area NFET´s
Author :
Hook, Terence B.
Author_Institution :
IBM Corp., Essex Junction, VT, USA
fDate :
8/1/1999 12:00:00 AM
Abstract :
When a 0.35-μm CMOS technology was introduced into manufacturing, a small fraction of the tested devices exhibited symptoms of source/drain underlap, despite the fact that all other monitors were well within the design control limits. Additional measurements showed variable overlap on various monitor structures on the same chip. The specific formulation of an HF wet clean was shown to be responsible for the underlapped devices, and the problem was eliminated by altering this process step. High-volume manufacturing data are presented to show the problem and the solution
Keywords :
CMOS logic circuits; hot carriers; integrated circuit manufacture; integrated circuit reliability; surface cleaning; 0.35 micron; CMOS technology; design control limits; high-volume manufacturing data; large junction area NFET; monitor structures; spurious source/drain underlap; wet clean; CMOS logic circuits; CMOS technology; Capacitance measurement; Current measurement; Logic devices; Manufacturing; Semiconductor device manufacture; Stress; Substrates; Testing;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
