Title :
A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC
Author :
Kalter, Howard L. ; Stapper, Charles H. ; Barth, John E., Jr. ; Dilorenzo, John ; Drake, Charles E. ; Fifield, John A. ; Kelley, Gordon A., Jr. ; Lewis, Scott C. ; Van Der Hoeven, Willem B. ; Yankosky, James A.
Author_Institution :
IBM Gen. Technol. Div., Essex Junction, VT, USA
fDate :
10/1/1990 12:00:00 AM
Abstract :
A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described. It can be packaged as a 2-Mb×8, 4-Mb×4, 8-Mb×2, or 16-Mb×1 DRAM, And is capable of operating in fast page mode, static column mode, or toggle mode. Speed and flexibility are achieved by a pipeline layout and on-chip SRAMs that buffer entire ECC words. The use of redundant word and bit lines in conjunction with the ECC produces a synergistic fault-tolerance effect
Keywords :
CMOS integrated circuits; DRAM chips; circuit reliability; error correction; fault tolerant computing; pipeline processing; redundancy; 16 Mbit; 3.3 V; 5 V; 50 ns; CMOS IC; DRAM; RAS/CAS addressing; error-correcting code; fast page mode; fault-tolerance; on-chip SRAMs; onchip ECC; pipeline layout; redundant bit lines; redundant word lines; static column mode; toggle mode; Content addressable storage; Density estimation robust algorithm; Error correction codes; Fault tolerance; Integrated circuit manufacture; Packaging; Pipelines; Power supplies; Random access memory; Redundancy;
Journal_Title :
Solid-State Circuits, IEEE Journal of
