• DocumentCode
    1534801
  • Title

    Detectability of CMOS stuck-open faults using random and pseudorandom test sequences

  • Author

    Sastry, Sarma ; Breuer, Michael

  • Author_Institution
    Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
  • Volume
    7
  • Issue
    9
  • fYear
    1988
  • fDate
    9/1/1988 12:00:00 AM
  • Firstpage
    933
  • Lastpage
    946
  • Abstract
    An analysis is presented of CMOS stuck-open faults tested with a pseudorandom test sequence, i.e. a test sequence consisting of some or all of the 2N test patterns generated by a modified N-bit linear-feedback shift register (LFSR). Such a scheme is viewed as testing without replacement. When all 2N test patterns are applied, then such a test sequence is called a pseudorandom exhaustive test sequence (PRETS). The alternative scheme is called random testing, which corresponds to sampling the population of test vectors with replacement. It is shown that some stuck-open faults require a single test vector of their detection, while most require an ordered pair of test vectors. A PRETS will detect all stuck-open faults that require a single test vector, but may not necessarily detect all faults that require an ordered pair of test vectors. The results obtained under pseudorandom testing are compared with results obtained under random testing
  • Keywords
    CMOS integrated circuits; automatic testing; combinatorial circuits; integrated circuit testing; integrated logic circuits; logic testing; probability; CMOS; asymptotic formulae; built-in testing; builtin self test; combinational networks; exhaustive test sequence; fault coverage estimation; linear-feedback shift register; pseudorandom test sequences; random test sequence; random testing; replacement; stuck-open faults; test vectors; Automatic testing; Built-in self-test; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Test pattern generators; Vectors;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.7792
  • Filename
    7792