Stress-Induced Via Voiding in a 130-nm CMOS Imager Process

This paper provides a detailed and systematic analysis of the mechanisms inducing voiding during high-temperature reliability tests in aluminum via holes in a 130-nm process for CMOS imagers. Finite-element simulations have been performed to derive the mechanical-stress profile in the examined structures, while a set of physical measurements and microscopy techniques have been used to analyze the microstructure of the polycrystalline materials that fill the via holes. Experiments have been designed on the basis of the simulation results, and consisted of some simple changes to the fabrication-technology steps. The failure rate on a few hundreds of samples was checked and compared with reference samples of the production line. The test allowed suggesting variations to a few process parameters that proved to be effective.