Dipole heterostructure field-effect transistor

It is proposed to reduce the gate current by using a dipole created by two doped planes, n/sup ++/ and p/sup ++/, in charge control layer, dipole heterostructure field-effect transistors (dipole HFETs) fabricated in AlGaAs/GaAs use doped p/sup ++/ and n/sup ++/ planes in the charge control AlGaAs layer to form a dipole that provides a considerably larger barrier between the channel and the gate than that in conventional heterostructure FETs. This leads to a reduction of the forward-biased gate current in enhancement-mode n-channel devices, by a factor of approximately 9 at 1.2 V in the experimental devices, when compared with equivalent conventional HFETs. A much broader transconductance region, in the range of 0.5-2.5-V gate bias, a higher maximum drain current, and no negative transconductance are also observed. A comparison between the gate current-voltage characteristics of conventional and dipole HFETs for 1- mu m-long and 10- mu m-wide gate devices is given. The measured results clearly indicate that a dipole HFET has a much smaller gate leakage current leading to superior performance of enhancement-mode devices. The results demonstrate the effectiveness of the dipole layer concept for digital HFET devices.<>