Title :
On/off current ratio in P-channel poly-Si MOSFETs: dependence on hot-carrier stress conditions
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
Stress effects on poly-Si PMOS devices are investigated, and stress is related to the improvement or degradation of PMOS on/off current ratio. P-channel polysilicon MOSFETs have been stressed in the saturation and off-state regimes. Both the drive (on) current and leakage (off) current can be either increased or decreased after particular bias stress. On/off current ratio can be decreased by a factor of 2 for a stress bias of V/sub GS/=V/sub DS/=-11 V, but can be increased by a factor of 50 for a stress bias of V/sub GS/=-2 V, V/sub DS/=-11 V. Two effects of bias stress have been identified in poly-Si PMOS devices for which the on/off current ratio can either be increased or decreased after stress bias depending on the value of stress bias V/sub GS/. These effects of room-temperature stress are proposed to be due to either trapping of hot electrons or hot-hole-induced donor-type interface state generation.<>
Keywords :
elemental semiconductors; hot carriers; insulated gate field effect transistors; leakage currents; semiconductor device testing; silicon; -11 V; -2 V; P-channel polysilicon MOSFETs; PMOS on/off current ratio; bias stress; drive current; hot electron trapping; hot-carrier stress conditions; hot-hole-induced donor-type interface state generation; leakage current; off-state regimes; room-temperature stress; saturation regimes; Current measurement; Degradation; Hot carriers; Interface states; Leakage current; MOS devices; MOSFETs; Plasma measurements; Plasma temperature; Stress measurement;
Journal_Title :
Electron Device Letters, IEEE
