• DocumentCode
    1535653
  • Title

    Low-power self-timed circuit design technique

  • Author

    Shyh-Jye Jou

  • Author_Institution
    Dept. of Electr. Eng., Nat. Central Univ., Chung-Li
  • Volume
    33
  • Issue
    2
  • fYear
    1997
  • fDate
    1/16/1997 12:00:00 AM
  • Firstpage
    110
  • Lastpage
    111
  • Abstract
    An implementation of self-timed circuits whose hardware and control signals are significantly reduced is proposed. A globally asynchronous locally synchronous design using the proposed self-timed circuits is also demonstrated. A design example shows that in this implementation less power is consumed with only a small circuit overhead
  • Keywords
    logic design; circuit overhead; globally asynchronous locally synchronous design; power consumption; self-timed circuit design;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19970110
  • Filename
    579406
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1535653