DocumentCode
1535716
Title
Forward-looking fault simulation for improved static compaction
Author
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume
20
Issue
10
fYear
2001
fDate
10/1/2001 12:00:00 AM
Firstpage
1262
Lastpage
1265
Abstract
Fault simulation of a test set in an order different from the order of generation (e.g., reverse- or random-order fault simulation) is used as a fast and effective method to drop unnecessary tests from a test set in order to reduce its size. We propose an improvement to this type of fault simulation process that makes it even more effective in reducing the test-set size. The proposed improvement allows us to drop tests without simulating them based on the fact that the faults they detect will be detected by tests that will be simulated later, hence the name of the improved procedure: forward-looking fault simulation. We present experimental results to demonstrate the effectiveness of the proposed improvement
Keywords
automatic testing; combinational circuits; fault simulation; logic testing; sequential circuits; forward-looking fault simulation; random-order fault simulation; static compaction; test set; test-set size; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational modeling; Electrical fault detection; Fault detection; Fault diagnosis; Sequential analysis; Sequential circuits;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.952743
Filename
952743
Link To Document