Title :
20Gbit/s regenerative receiver IC using InP/InGaAs double-heterostructure bipolar transistors
Author :
Sano, E. ; Kurishima, K. ; Yamahata, S.
Author_Institution :
NTT Syst. Electron. Labs., Atsugi, Japan
fDate :
1/16/1997 12:00:00 AM
Abstract :
A regenerative receiver IC, constructed with a preamplifier, post-amplifier automatic offset controller, PLL-based timing recovery circuit, and D-type flipflop, has been successfully fabricated. 20 Gbit/s error-free operation for an input dynamic range of 13 dB was achieved with a power dissipation of 0.6 W
Keywords :
III-V semiconductors; gallium arsenide; heterojunction bipolar transistors; indium compounds; integrated optoelectronics; optical receivers; 0.6 W; 20 Gbit/s; D-type flipflop; InP-InGaAs; InP/InGaAs double-heterostructure bipolar transistor; PLL timing recovery circuit; post-amplifier automatic offset controller; preamplifier; regenerative receiver IC;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19970101
