Title :
Work-efficient routing algorithms for rearrangeable symmetrical networks
Author :
Cam, Hasan ; Fortes, José A B
Author_Institution :
Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
fDate :
7/1/1999 12:00:00 AM
Abstract :
The work performed by a parallel algorithm is the product of its running time and the number of processors it requires. This paper presents work-efficient (or cost-optimal) routing algorithms to determine the switch settings for realizing permutations on rearrangeable symmetrical networks such as Benes and the reduced Ω NΩN-1. These networks have 2n-1 stages with N=2n inputs/outputs, each stage consisting of N/2 crossbar switches of size (2×2). Previously known parallel routing algorithms for a rearrangeable network with N inputs determine the states of all switches recursively in O(n) iterations using N processors. Each iteration determines the switch settings of at most two stages of the network and requires at least O(n) time on a computer of N processors, regardless of the type of its interconnection network. Hence, the work of any previously known parallel routing algorithm equals at least O(Nn2) for setting up all the switches of a rearrangeable network. The new routing algorithms run on a computer of p processors, 1⩽p⩽N/n, and perform work O(Nn). Moreover, because the range of p is large, the new routing algorithms do not have to be changed in case some processors become faulty
Keywords :
computational complexity; multiprocessor interconnection networks; parallel algorithms; N/2 crossbar switches; parallel algorithm; rearrangeable network; rearrangeable symmetrical networks; work-efficient routing algorithms; Algorithm design and analysis; Computer networks; Concurrent computing; Intelligent networks; Multiprocessor interconnection networks; Parallel algorithms; Phase change random access memory; Routing; Switches; Symmetric matrices;
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on