DocumentCode :
1536188
Title :
ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs
Author :
Wang, Xin ; Guan, Xiaokang ; Fan, Siqiang ; Tang, He ; Zhao, Hui ; Lin, Lin ; Fang, Qiang ; Liu, Jian ; Wang, Albert ; Yang, Lee
Author_Institution :
Dept. of Electr. Eng., Univ. of California, Riverside, CA, USA
Volume :
58
Issue :
7
fYear :
2011
fDate :
7/1/2011 12:00:00 AM
Firstpage :
2736
Lastpage :
2743
Abstract :
Electrostatic discharge (ESD) failure is a major reliability problem, and ESD protection is an emerging design challenge for radio-frequency (RF) integrated circuits demanding extremely high reliability for wireless applications in harsh environments. This paper reports the design and optimization of a 5-kV ESD-protected 2.4-GHz power amplifier (PA) circuit in a 0.18-μm RFCMOS technology. A new mixed-mode ESD simulation-design method and an accurate RF ESD characterization technique are used to minimize the inevitable ESD-induced parasitic effects, which can significantly degrade PA circuit performance. A novel ESD-aware PA design technique is utilized to optimize whole-chip ESD+PA performance. Experiments show that conventional ESD protection can seriously affect the PA circuit, while optimized ESD protection may resolve such a problem. The optimized ESD-protected PA circuit achieves good whole-chip performance, including 5-kV ESD protection, a linear output of 13.5 dBm, a gain of 20.2 dB, and a power-added efficiency of ~ 18%, all favorable in the same design category.
Keywords :
CMOS analogue integrated circuits; circuit optimisation; electrostatic discharge; failure analysis; integrated circuit design; integrated circuit reliability; power amplifiers; protection; radiofrequency integrated circuits; ESD failure; ESD-aware PA design technique; ESD-induced parasitic effects; ESD-protected power amplifier design; PA circuit performance; RF ESD characterization technique; RFCMOS technology; RFIC; conventional ESD protection; electrostatic discharge failure; frequency 2.4 GHz; gain 20.2 dB; harsh environments; mixed-mode ESD simulation-design method; optimization; optimized ESD protection; optimized ESD-protected PA circuit; power amplifier circuit; power-added efficiency; radio-frequency integrated circuits; size 0.18 mum; voltage 5 kV; whole-chip ESD+PA performance; wireless applications; Circuit optimization; Circuit simulation; Degradation; Design optimization; Electrostatic discharge; High power amplifiers; Power amplifiers; Protection; Radio frequency; Radiofrequency amplifiers; Electrostatic discharge (ESD); integrated circuit (IC); power amplifier (PA); radio frequency (RF);
fLanguage :
English
Journal_Title :
Industrial Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0046
Type :
jour
DOI :
10.1109/TIE.2010.2057234
Filename :
5510166
Link To Document :
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