DocumentCode
1536413
Title
Test resource partitioning for SOCs
Author
Chandra, Anshuman ; Chakrabarty, Krishnendu
Author_Institution
Duke Univ., Durham, NC, USA
Volume
18
Issue
5
fYear
2001
Firstpage
80
Lastpage
91
Abstract
A new test-resource-partitioning approach, based on test data compression and on-chip decompression, reduces data volume, decreases testing time, and accommodates slower (less expensive) testers without decreasing test duality
Keywords
logic testing; microprocessor chips; SOCs; test data compression; test duality; test-resource-partitioning; testers; testing time; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit testing; Compaction; Decoding; Hardware; Logic testing; Random access memory; Test data compression;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.953275
Filename
953275
Link To Document