Title :
Online and offline BIST in IP-core design
Author :
Benso, Alfredo ; Chinsano, S. ; Di Natale, Giorgio ; Prinetto, Paolo ; Bodoni, Monica Lobetti
Author_Institution :
Politecnico di Torino, Italy
Abstract :
This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraints
Keywords :
SRAM chips; built-in self test; BIST; IP-core design; SRAM intellectual-property core; code-based fault detection; fault avoidance; fault-latency reduction; reliability constraints; telecommunication applications; Automatic testing; Built-in self-test; Computer network reliability; Degradation; Delay; Fault detection; Random access memory; Read-write memory; Signal detection; System testing;
Journal_Title :
Design & Test of Computers, IEEE
