DocumentCode
1536419
Title
Online and offline BIST in IP-core design
Author
Benso, Alfredo ; Chinsano, S. ; Di Natale, Giorgio ; Prinetto, Paolo ; Bodoni, Monica Lobetti
Author_Institution
Politecnico di Torino, Italy
Volume
18
Issue
5
fYear
2001
Firstpage
92
Lastpage
99
Abstract
This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraints
Keywords
SRAM chips; built-in self test; BIST; IP-core design; SRAM intellectual-property core; code-based fault detection; fault avoidance; fault-latency reduction; reliability constraints; telecommunication applications; Automatic testing; Built-in self-test; Computer network reliability; Degradation; Delay; Fault detection; Random access memory; Read-write memory; Signal detection; System testing;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.953276
Filename
953276
Link To Document