Development of low power multi channel interpolator for system on chip in 4G application

1, 2, 4, 8,16,32,64, 128 channel UP convertor implemented in GSM has been designed and developed in this paper. The convertor is implemented using CM FIR filter requiring less routing area, less static and dynamic power and finally, providing high sampling rate conversion with large bandwidth . The system developed is superior to direct form based down convertor in terms of high power consumption, large delay& limited channels up to 128 channels. We have achieved large sampling rate conversion with large bandwidth & low power consumption using combination of CIC & MAC architecture of FIR filter. The 8 channel model consumes 3231.7mW (static power 3055.1mW & dynamic 176.6mW). After applying three different routing & placement algorithms on 8 channels model namely global routing, channel routing and river routing the power consumed results 2744.1mW (static power 2612 mW & dynamic 132.1mW) , 193.7mW (static power 71.4mW & dynamic 122.3mW) and 189..6mW (static power 67.6mW& dynamic 122 mW) respectively. In an extended work the authors have tried and successfully executed the model and system for 128 channels for 4G applications. The proposed model is first designed on simulink platform using Xilinx blackest and then it is transferred on FPGA platform using system generator. The complete circuit is synthesized, implemented, simulated using Xilinx design suite.