Title :
A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter
Author :
Lee, Chang-Hyeon ; McClellan, Kelly ; Choma, John, Jr.
Author_Institution :
Wireless Commun. Div., Conexant Syst. Inc., Newport Beach, CA, USA
fDate :
10/1/2001 12:00:00 AM
Abstract :
A 500-MHz supply-noise-insensitive CMOS phase-locked loop (PLL) with a voltage regulator using a capacitive dc-dc converter (VRCC) achieves a jitter level of 30-ps RMS for quiet supply, and 42-ps RMS for 600-mV supply noise, with a locking range of 110 to 850 MHz. The worst-case power supply noise rejection (PSNR) using the VRCC shows -45 dB in the mid-frequency band. The circuit is fabricated in a 0.35-μm 3.3-V standard digital CMOS process and occupies 2.3 mm2. The power consumption at 3.3 V including buffer is 42 mW at 500 MHz
Keywords :
CMOS analogue integrated circuits; DC-DC power convertors; integrated circuit noise; jitter; phase locked loops; voltage regulators; 0.35 micron; 3.3 V; 42 mW; 500 MHz; CMOS PLL; DC-DC capacitive converter; jitter level; locking range; power consumption; power supply noise rejection; supply-noise-insensitive phase-locked loop; voltage regulator; Circuit noise; DC-DC power converters; Jitter; Noise level; PSNR; Phase locked loops; Phase noise; Power supplies; Regulators; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
