A fast-lock mixed-mode DLL using a 2-b SAR algorithm

Author

Dehng, Guang-Kaai ; Lin, Jyh-Woei ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

36

Issue

10

fYear

2001

fDate

10/1/2001 12:00:00 AM

Firstpage

1464

Lastpage

1471

Abstract

In this paper, a fast-lock mixed-mode delay-locked loop (MMDLL) is presented. The digital part of the MMDLL utilizes a 2-b SAR algorithm to achieve short lock time compared to the conventional RDLL, CDLL, and SARDLL, while the analog part helps to reduce the residue phase error introduced by the digital part and improve the output jitter performance. The measured RMS and peak-to-peak jitters and the static phase error are 6.6, 47, and 12.4 ps, respectively, for a 100-MHz input clock. The power consumption is 15.8 mW in the locked state at a 2.7-V supply voltage. The maximum lock time is 13.5 clock cycles (135 ns) when the residue phase error is within 1 LSB (156 ps)

Keywords

delay lock loops; mixed analogue-digital integrated circuits; 100 MHz; 15.8 mW; 2 bit; 2.7 V; fast-lock mixed-mode delay-locked loop; jitter; phase error; power consumption; successive approximation register algorithm; Automatic control; Clocks; Delay effects; Delay lines; Digital control; Digital systems; Feedback loop; Jitter; Synchronization; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.953474

Filename

953474