Linear phase decimation and interpolation filters for high-speed applications

A novel hardware realisation for linear phase decimation and interpolation FIR filters, exploiting the symmetry of the coefficients to reduce the number of multipliers, is described. Combining the multiplications, leads to contra-dataflow or folded filter structures in which simple pipelining is limited, because of the opposite directions of the data flows. It is shown that these structures can be transformed into new filter structures, which allow conventional pipelining to relax the timing demands for high-speed applications