Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs

Author

Kanda, Kouichi ; Nose, Kouichi ; Kawaguchi, Hiroshi ; Sakurai, Takayasu

Author_Institution

Center for Collaborative Res., Tokyo Univ., Japan

Volume

36

Issue

10

fYear

2001

fDate

10/1/2001 12:00:00 AM

Firstpage

1559

Lastpage

1564

Abstract

In sub-1-V CMOS designs, especially around 0.5-V CMOS designs, on-state drain current of MOSFETs shows positive temperature dependence, being different from the negative temperature dependence in the conventional voltage designs. Combined with low threshold voltage less than 0.2 V, the possibility of temperature instability increases. This paper describes possible temperature instabilities in the low-voltage regime by using circuit simulation environments incorporating temperature change in time and experiments using MOSFETs and the 32-bit adder circuit in quarter-micrometer CMOS technology with a low threshold voltage of 0.25 V

Keywords

CMOS logic circuits; VLSI; adders; integrated circuit design; low-power electronics; 0.25 V; 32 bit; CMOS VLSI; adder; circuit simulation; drain current; low-voltage design; temperature dependence; temperature instability; threshold voltage; CMOS technology; Circuit simulation; Degradation; Delay; MOS devices; MOSFETs; Temperature dependence; Temperature measurement; Threshold voltage; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.953485

Filename

953485