Title :
ItaniumTM Processor system bus design
Author :
Iikbahar, A. ; Venkataraman, Srinivas ; Muljono, Harry
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fDate :
10/1/2001 12:00:00 AM
Abstract :
This paper presents the design of the ItaniumTM Processors system bus interface achieving a peak data bandwidth of 2.1 GB/s in a glueless four-way multiprocessing system. A source-synchronous data bus with differential strobes enables this high bandwidth. Topics covered in this paper include optimization technique for the system topology, CPU package, signaling protocol, and I/O circuits. Highly accurate modeling and validation methodologies enable a good correlation of experimental results with simulation data
Keywords :
microprocessor chips; multiprocessing systems; system buses; 2.1 GB/s; CPU package; I/O circuit; Itanium Processor; data bandwidth; differential strobe; glueless four-way multiprocessing system; signaling protocol; source-synchronous data bus; system bus interface design; system topology optimization; Bandwidth; Central Processing Unit; Circuit topology; Clocks; Dielectric substrates; Integrated circuit interconnections; Packaging; Process design; Signal processing; System buses;
Journal_Title :
Solid-State Circuits, IEEE Journal of
