DocumentCode
1536955
Title
Power estimation in adiabatic circuits: a simple and accurate model
Author
Alioto, Massimo ; Palumbo, Gaetano
Author_Institution
Dept. of Electr. Electron. & Syst., Catania Univ., Italy
Volume
9
Issue
5
fYear
2001
Firstpage
608
Lastpage
615
Abstract
A simple procedure to evaluate the energy consumption of adiabatic gate circuits is proposed and validated. The proposed strategy is based on a linearization of the circuit and simplifying the analytical result obtained on the equivalent network. The approach leads to simple relationships which can be used for a pencil-and-paper evaluation or implemented on software. The accuracy of the results is validated by means of Spice simulations on an adiabatic full adder designed with a 0.8 /spl mu/m technology.
Keywords
CMOS digital integrated circuits; SPICE; integrated circuit design; power consumption; 0.8 /spl mu/m technology; 0.8 mum; Spice simulation; adiabatic circuits; adiabatic full adder; energy consumption; model; power estimation; Adders; Capacitance; Circuit simulation; Clocks; Energy consumption; Mesh networks; Resistors; Shape; Switches; Switching circuits;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.953495
Filename
953495
Link To Document