Design and Implementation of Seamless Rate Adaptive Decoder

Seamless rate adaptation (SRA) is one of the promising rate adaptive schemes for wireless communication system. However, the high complexity of decoding hinders its application. We propose an optimized Application-specific integrated circuit (ASIC) design and implementation for SRA decoder in this paper. In order to balance speed and resource consumption, a partial parallel architecture is used in SRA decoder, which consists of 8x8 parallel computation unit, each computation unit calculates decoding metrics in pipelining way. In order to further improve the throughput of the decoder, a parallel structure for multivariable Jacobian logarithm approximation is designed. We also illustrate how fixed-point SRA decoder is designed. Numerical simulation shows the decoding performance of our design has neglect able performance loss. The optimized decoder ASIC can achieve 84Mbps throughput running at 300Mhz, occupying an area of 5 5mm2 and consuming power 4.21W. Compared to our previous design in FPGA, the throughput of this ASIC increases about 17:5 times.